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| (R) HCF4510B HCF4516B PRESETTABLE UP/DOWN COUNTERS MEDIUM SPEED OPERATION fCL = 8MHz TYP. AT 10V s SYNCHRONOUS INTERNAL CARRY PROPAGATION s RESET AND PRESET CAPABILITY s QUIESCENT CURRENT SPECIFIED TO 15V s 5V, 10V, AND 15V PARAMETRIC RATINGS s INPUT CURRENT OF 100nAAT 15V AND 25C s 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS DEVICES" s DIP ORDER CODES PACKAGE DIP SOP TUBE HCF45XXBEY HCF45XXBM1 SOP T&R HCF45XXM013TR DESCRIPTION The HCF4510B and HCF4516B are monolithic integrated circuits available in 16-lead dual in-line plastic and plastic micro package. The HCF4510B Presettable BCD Up/Down Counter and the HCF4516B Presettable Binary Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The HCF4510B will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, PIN CONNECTION and a maximum of four clock pulses in the down mode. If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage. The HCF4510B and HCF4516B can be loaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. March 2000 1/12 HCF4510B/4515B FUNCTIONAL DIAGRAM TRUTH TABLE CL X CI 1 0 0 X X X= Don't care U/D X 1 0 X X PE 0 0 0 1 X R 0 0 0 0 1 Actio n No Count Count Up Count Down Preset Reset X X ABSOLUTE MAXIMUM RATING Symbol VDD * Vi II Ptot Supply Voltage Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package Temperature Range Operating Temperature Storage Temperature Parameter Value -0.5 to +18 -0.5 to VDD + 0.5 10 200 100 -40 to +85 -65 to +150 Unit V V mA mW mW o o Top Tstg C C Stresses above those listedunder "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation ofthe device atthese or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratingconditions for external periods may affect device reliability. * Allvoltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 15 0 to VDD -40 to +85 Unit V V o C 2/12 HCF4510B/4516B LOGIC DIAGRAMS 4510B 4516B 3/12 HCF4510B/4515B TIMING DIAGRAMS 4510B 4516B 4/12 HCF4510B/4516B STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions) Symb ol Parameter VI (V) IL Quiescent Current 0/5 0/10 0/15 VOH Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Output Drive Current 0/5 0/5 0/10 0/15 IOL Output Sink Current 0/5 0/10 0/15 IIH, IIL CI Input Leakage Current Input Capacitance 0/15 0/5 0/10 0/15 VOL 5/0 10/0 15/0 VIH 0.5/4.5 1/9 1.5/13.5 VIL 4.5/0.5 9/1 13.5/1.5 IOH 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Any Input Any Input <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 T est Cond it ios VO (V) Valu e Un it |IO | V DD -40 oC 25 o C 85 o C (A) (V) Min. Max. Min. T yp. Max. Min . Max. 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 15 -1.53 -0.52 -1.3 -3.6 0.52 1.3 3.6 0.3 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10 5 -5 20 40 80 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 4.95 9.95 14.95 0.02 0.02 0.02 20 40 80 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 0.3 7.5 150 300 600 V 0.05 0.05 0.05 V 1.5 3 4 mA V V A mA 1 A pF TheNoise Margin for both "1" and "0" level is: 1V min.withV DD = 5 V, 2 V min.with VDD = 10 V, 2.5 V min. with VDD = 15 V 5/12 HCF4510B/4515B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 oC, CL = 50 pF, RL = 200 K, typical temperaturecoefficent for all VDD values is 03 %/oC, all input rise and fall times= 20 ns) Symb ol Parameter T est Cond ition s V DD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value Typ. Max. 200 100 75 210 105 80 240 120 90 125 60 50 320 160 125 100 50 40 4 8 11 400 200 150 420 210 160 480 240 180 250 120 100 640 320 250 200 100 80 Un it tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tTHL tTLH fMAX Propagation Delay Time Clock to Q Output ns Propagation Delay Time Preset or Reset to Q Output Propagation Delay Time Clock to Carry Out ns ns Propagation Delay Time Carry In to Carry Out Propagation Delay Time Preset or Reset to Carry Out Transition Time ns ns ns Max Clock Frequency 2 4 5.5 150 75 60 150 80 60 MHz tW Clock Pulse Width ns Preset Enable or Reset Removal Time (1) ns 15 5 5 tr, tf Clock Rise and Fall Time (2) s tsetup Carry In Setup Time tsetup Up Down Setup Time tW Preset Enable or Reset Pulse Width 130 60 45 360 160 110 220 100 75 ns ns ns (1) Timerequired after the falling edge of the reset or preset enable inuts before the rising edge ofthe clock will trigger the counter (similar to setup time). (2) Ifmore than unit is cascated in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed propagation delay at 15pF and the transition timeof the carry output driving stage ofthe estimated capacitive load. 6/12 HCF4510B/4516B Typical Output Low (sink) Current Characteristics. Minimum Output Low (sink) Current Characteristics. Typical Output High (source) Current Characteristics. Minimum Output High (source) Current Characteristics. Typical Propagation Delay Time vs. Load Capacitance for Clock to Q Output. Typical Maximum Clock Input Frequency vs. Supply Voltage. 7/12 HCF4510B/4515B Typical Transition Time vs. Load Capacitance. Typical Dynamic Power Dissipation vs. Frequency. TYPICAL APPLICATIONS TYPICAL 16-CHANNEL, 10 BIT DATA ACQUISITION SYSTEM Thisacquisition system can be operated in the random access mode by jamming in the channel number at the present inputs, or in the sequential mode by clocking the HCF4516B. 8/12 HCF4510B/4516B CASCADING COUNTER PACKAGES TEST CIRCUITS Quiescent Device Current. Noise Immunity. Input Leakage Current. Power Dissipation and Input Waveform. 9/12 HCF4510B/4515B Plastic DIP-16 (0.25) MECHANICAL DATA mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX. DIM. P001C 10/12 HCF4510B/4516B SO-16 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 P013H 11/12 HCF4510B/4515B Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 12/12 |
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